ATS
2004
IEEE
14 years 3 months ago
2004
IEEE
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...
ATS
2005
IEEE
14 years 5 months ago
2005
IEEE
Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to...
ASPDAC
2006
ACM
14 years 5 months ago
2006
ACM
Abstract— For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation...
VLSID
2004
IEEE
14 years 12 months ago
2004
IEEE
