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    TVLSI
    2008
    197views more  TVLSI 2008»
    Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology
    13 years 11 months ago
    Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology
    Download  atrak.usc.edu
    -- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
    Behnam Amelifard, Farzan Fallah, Massoud Pedram
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    TVLSI
    2008
    102views more  TVLSI 2008»
    A Robust 4-PAM Signaling Scheme for Inter-Chip Links Using Coding in Space
    13 years 11 months ago
    A Robust 4-PAM Signaling Scheme for Inter-Chip Links Using Coding in Space
    Download  www.eecg.toronto.edu
    Abstract--Increasing demand for high-speed inter-chip interconnects requires faster links that consume less power. Channel coding can be used to lower the required signal-to-noise ...
    Kamran Farzan, David A. Johns
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    TVLSI
    2008
    169views more  TVLSI 2008»
    Energy-Aware Flash Memory Management in Virtual Memory System
    13 years 11 months ago
    Energy-Aware Flash Memory Management in Virtual Memory System
    Download  grid.ntu.edu.tw
    The traditional virtual memory system is designed for decades assuming a magnetic disk as the secondary storage. Recently, flash memory becomes a popular storage alternative for ma...
    Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng
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    TVLSI
    2008
    133views more  TVLSI 2008»
    Test Data Compression Using Selective Encoding of Scan Slices
    13 years 11 months ago
    Test Data Compression Using Selective Encoding of Scan Slices
    Download  people.ee.duke.edu
    We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...
    Zhanglei Wang, Krishnendu Chakrabarty
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    TVLSI
    2008
    176views more  TVLSI 2008»
    A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
    13 years 11 months ago
    A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
    Download  www.csee.usf.edu
    Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
    Venkataraman Mahalingam, N. Ranganathan, J. E. Har...
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    TVLSI
    2008
    157views more  TVLSI 2008»
    Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory
    13 years 11 months ago
    Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory
    Download  dtl.yonsei.ac.kr
    This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...
    Hyuk-Jun Lee, Eui-Young Chung
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    TVLSI
    2008
    111views more  TVLSI 2008»
    GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
    13 years 11 months ago
    GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
    Download  www.ece.ubc.ca
    This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
    Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...
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    TVLSI
    2008
    108views more  TVLSI 2008»
    Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
    13 years 11 months ago
    Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
    Download  access.ee.ntu.edu.tw
    To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo de...
    Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu
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    TVLSI
    2008
    151views more  TVLSI 2008»
    Guest Editorial Special Section on Design Verification and Validation
    13 years 11 months ago
    Guest Editorial Special Section on Design Verification and Validation
    Download  www.princeton.edu
    ion levels. The framework also supports the generation of test constraints, which can be satisfied using a constraint solver to generate tests. A compositional verification approac...
    I. Harris, D. Pradhan
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    TVLSI
    2008
    86views more  TVLSI 2008»
    Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking
    13 years 11 months ago
    Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking
    Download  users.ece.gatech.edu
    B. Taskin, Bo Hong
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