Sciweavers

TVLSI
2008
102views more  TVLSI 2008»
15 years 27 days ago
A Robust 4-PAM Signaling Scheme for Inter-Chip Links Using Coding in Space
Abstract--Increasing demand for high-speed inter-chip interconnects requires faster links that consume less power. Channel coding can be used to lower the required signal-to-noise ...
Kamran Farzan, David A. Johns
133
Voted
TVLSI
2008
169views more  TVLSI 2008»
15 years 27 days ago
Energy-Aware Flash Memory Management in Virtual Memory System
The traditional virtual memory system is designed for decades assuming a magnetic disk as the secondary storage. Recently, flash memory becomes a popular storage alternative for ma...
Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng
TVLSI
2008
133views more  TVLSI 2008»
15 years 27 days ago
Test Data Compression Using Selective Encoding of Scan Slices
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...
Zhanglei Wang, Krishnendu Chakrabarty
121
Voted
TVLSI
2008
176views more  TVLSI 2008»
15 years 27 days ago
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
Venkataraman Mahalingam, N. Ranganathan, J. E. Har...
TVLSI
2008
157views more  TVLSI 2008»
15 years 27 days ago
Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...
Hyuk-Jun Lee, Eui-Young Chung
TVLSI
2008
111views more  TVLSI 2008»
15 years 27 days ago
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...
TVLSI
2008
108views more  TVLSI 2008»
15 years 27 days ago
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo de...
Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu
103
Voted
TVLSI
2008
151views more  TVLSI 2008»
15 years 27 days ago
Guest Editorial Special Section on Design Verification and Validation
ion levels. The framework also supports the generation of test constraints, which can be satisfied using a constraint solver to generate tests. A compositional verification approac...
I. Harris, D. Pradhan
86
Voted
TVLSI
2008
90views more  TVLSI 2008»
15 years 27 days ago
A Special-Purpose Architecture for Solving the Breakpoint Median Problem
Abstract--In this paper, we describe the design for a co-processor for whole-genome phylogenetic reconstruction. Our current design performs a parallelized breakpoint median comput...
Jason D. Bakos, Panormitis E. Elenis