Abstract--In this paper, we describe the design for a co-processor for whole-genome phylogenetic reconstruction. Our current design performs a parallelized breakpoint median comput...
With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Max...
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors...
Abstract--A SMART repeater is proposed for driving capacitively-coupled, global-length on-chip interconnects that alters its drive strength dynamically to match the relative bit pa...
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search...
Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is ra...
Abstract--The quantum-dot cellular automata (QCA) model offers a novel nano-domain computing architecture by mapping the intended logic onto the lowest energy configuration of a co...
Up to 53% of the time spent on testing current Intel microprocessors is needed to test on-chip caches, due to the high complexity of memory tests and to the large amount of transis...
Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Sta...