High-Performance Power Grids For Nanometer Technologies

With shrinking noise margins and increasing numbers of on-chip noise sources, power grid design has become a critical performance determinant. This paper presents an overview of recent techniques for the analysis and optimization of supply networks, and discusses future trends in power grid design.

• Type: Conference
• Year: 2004
• Where: VLSID
• Authors: Sachin S. Sapatnekar
• Keywords: Computer Architecture, Critical Performance Determinant, On-chip Noise Sources, Power Grid Design, VLSID 2004