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VLSID
2004
IEEE
73views VLSI» more  VLSID 2004»
14 years 11 months ago
Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling
Reduction of worst-case delay and delay uncertainty due to capacitive coupling is a still unsolved problem in physical design. We describe a routing only layout solution - swizzli...
Puneet Gupta, Andrew B. Kahng
VLSID
2004
IEEE
142views VLSI» more  VLSID 2004»
14 years 11 months ago
Dynamic Noise Margin: Definitions and Model
Dynamic noise analysis is greatly needed in place of traditional static noise analysis due to the ever increasingly stringent design requirement for VLSI chips based on very deep ...
Li Ding 0002, Pinaki Mazumder
VLSID
2004
IEEE
119views VLSI» more  VLSID 2004»
14 years 11 months ago
Bridge Over Troubled Wrappers: Automated Interface Synthesis
System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often ...
Vijay D'Silva, S. Ramesh, Arcot Sowmya
VLSID
2004
IEEE
112views VLSI» more  VLSID 2004»
14 years 11 months ago
Designing Leakage Aware Multipliers
Power consumption has become a major design limiter. With the continued reduction of threshold voltages, optimizing leakage energy consumption is becoming increasingly important. ...
M. DeRenzo, Mary Jane Irwin, Narayanan Vijaykrishn...
VLSID
2004
IEEE
292views VLSI» more  VLSID 2004»
14 years 11 months ago
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
Jeremy Chan, Sri Parameswaran
VLSID
2004
IEEE
119views VLSI» more  VLSID 2004»
14 years 11 months ago
Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach
The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemming from requirements of the application an...
Jens Bieger, Sorin A. Huss, Michael Jung, Stephan ...
VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
14 years 11 months ago
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
Shabbir H. Batterywala, Narendra V. Shenoy
VLSID
2004
IEEE
93views VLSI» more  VLSID 2004»
14 years 11 months ago
Random Access Scan: A solution to test power, test data volume and test time
Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara