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DATE
2009
IEEE
167views Hardware» more  DATE 2009»
14 years 6 months ago
Analyzing the impact of process variations on parametric measurements: Novel models and applications
Abstract—In this paper we propose a novel statistical framework to model the impact of process variations on semiconductor circuits through the use of process sensitive test stru...
Sherief Reda, Sani R. Nassif
ICCAD
2003
IEEE
170views Hardware» more  ICCAD 2003»
14 years 8 months ago
Evaluation of Placement Techniques for DNA Probe Array Layout
DNA probe arrays have emerged as a core genomic technology that enables cost-effective gene expression monitoring, mutation detection, single nucleotide polymorphism analysis and ...
Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu ...
ICCAD
2005
IEEE
151views Hardware» more  ICCAD 2005»
14 years 8 months ago
Architecture and details of a high quality, large-scale analytical placer
Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just a few to ...
Andrew B. Kahng, Sherief Reda, Qinke Wang
ICCAD
2005
IEEE
122views Hardware» more  ICCAD 2005»
14 years 8 months ago
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
A priori wirelength estimation is concerned with predicting various wirelength characteristics before placement. In this work we propose a novel, accurate estimator of net lengths...
Andrew B. Kahng, Sherief Reda
ICCAD
2007
IEEE
158views Hardware» more  ICCAD 2007»
14 years 8 months ago
Strategies for improving the parametric yield and profits of 3D ICs
Cesare Ferri, Sherief Reda, R. Iris Bahar