Closed-Form Simulation and Robustness Models for SEU-Tolerant Design

— A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SPICEbased calibration of logic gates for a range of values of fanout, charge, and scale factor is presented. A full set of experimental results demonstrate that on average, the model is accurate to within 5% of the results obtained using SPICE with over 100X improvement in computational speed. Besides simulation and analysis of SEU-induced transients, the proposed model can be used to perform reliability-aware logic synthesis through the incorporation of robustness metrics to tune cell libraries.

• Type: Conference
• Year: 2005
• Where: VTS
• Authors: Kartik Mohanram
• Keywords: Linear Rc Model, Single-event Upsets, Voltage Transients, VTS 2005