14 search results - page 1 / 3 » Efficient Scan Chain Design for Power Minimization During Sc... |
ITC
2003
IEEE
14 years 4 days ago
2003
IEEE
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
ASPDAC
2006
ACM
14 years 26 days ago
2006
ACM
Abstract— For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation...
ISQED
2006
IEEE
14 years 27 days ago
2006
IEEE
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
ETS
2009
IEEE
13 years 4 months ago
2009
IEEE
Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current whic...
ICCD
2006
IEEE
14 years 3 months ago
2006
IEEE
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...