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VTS
1995
IEEE

Cyclic stress tests for full scan circuits

14 years 3 months ago
Cyclic stress tests for full scan circuits
To ensure the production of reliable circuits and fully testable unpackaged dies for MCMs burn-in, both dynamic and monitored, remains a feasible option. During this burn-in process the circuit needs to be stressed for an extended period of time. This requires computation of cyclic input sequences to stress the circuit. A taxanomy of stress related problems for full scan circuits is presented. It is shown that there are efficient ways to compute the sequences for most variations of monitored burn-in problems. The difficulty of computing stress tests for dynamic burn-in problems is discussed. Preliminary experimental results on ISCAS89 benchmark circuits are presented.
Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Jan
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1995
Where VTS
Authors Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel
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