TVLSI
2002
13 years 10 months ago
2002
: Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low...
GLVLSI
2003
IEEE
14 years 4 months ago
2003
IEEE
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
GLVLSI
2005
IEEE
14 years 4 months ago
2005
IEEE
—On-chip power distribution grids with multiple supply voltages are discussed in this paper. Two types of interdigitated and paired power distribution grids with multiple supply ...
ICPPW
2007
IEEE
14 years 5 months ago
2007
IEEE
We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-achip, in particular DSP systems, can greatly improve p...
ICCD
2002
IEEE
14 years 7 months ago
2002
IEEE
Multiple supply voltages, multiple transistor thresholds and transistor sizing could be used to reduce the power dissipation of digital blocks. This paper presents a framework for...
ICCD
2003
IEEE
14 years 7 months ago
2003
IEEE
— We model the power fluctuation as cycle-to-cycle power gradient and minimize the mean of the power gradients using ILP. We propose scheduling schemes for three modes of datapa...
DAC
2003
ACM
14 years 12 months ago
2003
ACM
Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best pow...