Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation

Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. However, the average dynamic power of a circuit optimized by a deterministic path balancing approach increases because the filtered glitches randomly start reappearing under the influence of process variation. Combining several existing techniques, we propose a new statistical mixed integer linear programming (MILP) formulation, which uses path balancing and dual-threshold techniques to statistically minimize the total power in glitch-free circuits considering process variation.

• Type: Conference
• Year: 2008
• Where: VLSID
• Authors: Yuanlin Lu, Vishwani D. Agrawal
• Keywords: Circuits Considering Process, Computer Architecture, Path Balancing Approach, Process Variation, VLSID 2008