A parallel IEEE P754 decimal floating-point multiplier

Decimal floating-point multiplication is important in many commercial applications including banking, tax calculation, currency conversion, and other financial areas. This paper presents a fully parallel decimal floating-point multiplier compliant with the recent draft of the IEEE P754 Standard for Floating-point Arithmetic (IEEE P754). The novelty of the design is that it is the first parallel decimal floating-point multiplier offering low latency and high throughput. This design is based on a previously published parallel fixed-point decimal multiplier which uses alternate decimal digit encodings to reduce area and delay. The fixed-point design is extended to support floating-point multiplication by adding several components including exponent generation, rounding, shifting, and exception handling. Area and delay estimates are presented that show a significant latency and throughput improvement with a substantial increase in area as compared to the only published IEEE P754 ...

• Type: Conference
• Year: 2007
• Where: ICCD
• Authors: Brian J. Hickmann, Andrew Krioukov, Michael J. Schulte, Mark A. Erle
• Keywords: Decimal Digit Encodings, Decimal Multiplier, Decimal floating-point Multiplier, Hardware, ICCD 2007