FPGA device and architecture evaluation considering process variations

Process variations in nanometer technologies are becoming an important issue for cutting-edge FPGAs with a multimillion gate capacity. Considering both die-to-die and withindie variations in effective channel length, threshold voltage, and gate oxide thickness, we first develop closed-form models of leakage and timing variations at the FPGA chip level. Experiments show that our models are within 3% from Monte Carlo simulation, and the leakage and delay variations can

• Type: Conference
• Year: 2005
• Where: ICCAD
• Authors: Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He
• Keywords: Delay Variations, Hardware, ICCAD 2005, Process Variations, Timing Variations