Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

19

ICCAD
2002
IEEE

favoriteEmaildiscussreport

127views Hardware» more ICCAD 2002»

Leakage power modeling and reduction with data retention

14 years 7 months ago

Leakage power modeling and reduction with data retention

Download eda.ee.ucla.edu

Weiping Liao, Joseph M. Basile, Lei He

Real-time Traffic

Hardware | ICCAD 2002 |

claim paper

Related Content

» Fundamental Data Retention Limits in SRAM Standby Experimental Results

» DRGcache a data retention gatedground cache for low power

» Fundamental Bounds on Power Reduction during DataRetention in Standby SRAM

» Low power SRAM techniques for handheld products

» Microarchitecture floorplanning for subthreshold leakage reduction

» Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits

» Leakage power reduction of embedded memories on FPGAs through location assignment

» Sleepy Stack Reduction of Leakage Power

» LeakageConscious ArchitectureLevel Power Estimation for Partitioned and PowerGated SRAM Ar...

Post Info
More Details (n/a)

Added	16 Mar 2010
Updated	16 Mar 2010
Type	Conference
Year	2002
Where	ICCAD
Authors	Weiping Liao, Joseph M. Basile, Lei He

Comments (0)