Sciweavers
Explore
Publications
Books
Software
Tutorials
Presentations
Lectures Notes
Datasets
Labs
Conferences
Community
Upcoming
Conferences
Top Ranked Papers
Most Viewed Conferences
Conferences by Acronym
Conferences by Subject
Conferences by Year
Tools
Sci2ools
International Keyboard
Graphical Social Symbols
CSS3 Style Generator
OCR
Web Page to Image
Web Page to PDF
Merge PDF
Split PDF
Latex Equation Editor
Extract Images from PDF
Convert JPEG to PS
Convert Latex to Word
Convert Word to PDF
Image Converter
PDF Converter
Community
Sciweavers
About
Terms of Use
Privacy Policy
Cookies
Free Online Productivity Tools
i2Speak
i2Symbol
i2OCR
iTex2Img
iWeb2Print
iWeb2Shot
i2Type
iPdf2Split
iPdf2Merge
i2Bopomofo
i2Arabic
i2Style
i2Image
i2PDF
iLatex2Rtf
Sci2ools
18
click to vote
ISMVL
2007
IEEE
favorite
Email
discuss
report
143
views
Hardware
»
more
ISMVL 2007
»
An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays
14 years 4 months ago
Download
www.lsi-cad.com
Tsutomu Sasao
Real-time Traffic
Artificial Intelligence
|
ISMVL 2007
|
claim paper
Related Content
»
Logic Synthesis and PlaceandRoute Environment for ORGAs
»
Design flow for optimizing performance in processor systems with onchip coarsegrain reconf...
»
Using RewritingLogic Notation for Funcional Verification in DataStream Based Reconfigurabl...
»
Mapping DSP applications on processor systems with coarsegrain reconfigurable hardware
»
A High Performance Application Representation for Reconfigurable Systems
»
Asynchronous circuit design on reconfigurable devices
»
Genetic Algorithm based Engine for DomainSpecific Reconfigurable Arrays
»
A SelfReconfigurable Gate Array Architecture
»
Generation of Design Suggestions for CoarseGrain Reconfigurable Architectures
more »
Post Info
More Details (n/a)
Added
04 Jun 2010
Updated
04 Jun 2010
Type
Conference
Year
2007
Where
ISMVL
Authors
Tsutomu Sasao
Comments
(0)
Researcher Info
Hardware Study Group
Computer Vision