Sciweavers

DAC
2002
ACM
16 years 7 months ago
A framework for evaluating design tradeoffs in packet processing architectures
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
Lothar Thiele, Matthias Gries, Samarjit Chakrabort...
DAC
2002
ACM
16 years 7 months ago
Congestion-driven codesign of power and signal networks
Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R....
DAC
2002
ACM
16 years 7 months ago
A factorization-based framework for passivity-preserving model reduction of RLC systems
We present a framework for passivity-preserving model reduction for RLC systems that includes, as a special case, the well-known PRIMA model reduction algorithm. This framework pr...
Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh
DAC
2002
ACM
16 years 7 months ago
Deriving a simulation input generator and a coverage metric from a formal specification
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a function...
Kanna Shimizu, David L. Dill
112
Voted
DAC
2002
ACM
16 years 7 months ago
RTL c-based methodology for designing and verifying a multi-threaded processor
Andrew Seawright, Arjuna Ekanayake, Barry M. Pangr...
DAC
2002
ACM
16 years 7 months ago
Combined BEM/FEM substrate resistance modeling
For present-day micro-electronic designs, it is becoming ever more important to accurately model substrate coupling effects. Basically, either a Finite Element Method (FEM) or a B...
Eelco Schrik, N. P. van der Meijs
DAC
2002
ACM
16 years 7 months ago
Unlocking the design secrets of a 2.29 Gb/s Rijndael processor
This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput ...
Patrick Schaumont, Henry Kuo, Ingrid Verbauwhede
DAC
2002
ACM
16 years 7 months ago
Transformation based communication and clock domain refinement for system design
The ForSyDe methodology has been developed for system level design. In this paper we present formal transformation methods for the refinement of an abstract and formal system mode...
Ingo Sander, Axel Jantsch