Sciweavers

134
Voted
DAC
2008
ACM
16 years 7 months ago
Automated transistor sizing for FPGA architecture exploration
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and...
Ian Kuon, Jonathan Rose
DAC
2008
ACM
16 years 7 months ago
A progressive-ILP based routing algorithm for cross-referencing biochips
Due to recent advances in microfluidics technology, digital microfluidic biochips and their associated CAD problems have gained much attention, most of which has been devoted to d...
Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang...
183
Voted
DAC
2008
ACM
16 years 7 months ago
Partial order reduction for scalable testing of systemC TLM designs
A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is nondeterministic. To leverage testing of a SystemC TLM design, we f...
Sudipta Kundu, Malay K. Ganai, Rajesh Gupta
DAC
2008
ACM
16 years 7 months ago
SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models
SystemCoDesigner is an ESL tool developed at the University of Erlangen-Nuremberg, Germany. SystemCoDesigner offers a fast design space exploration and rapid prototyping of behavi...
Christian Haubelt, Thomas Schlichter, Joachim Kein...
DAC
2008
ACM
16 years 7 months ago
On reliable modular testing with vulnerable test access mechanisms
In modular testing of system-on-a-chip (SoC), test access mechanisms (TAMs) are used to transport test data between the input/output pins of the SoC and the cores under test. Prio...
Lin Huang, Feng Yuan, Qiang Xu
DAC
2008
ACM
16 years 7 months ago
Bi-decomposing large Boolean functions via interpolation and satisfiability solving
Boolean function bi-decomposition is a fundamental operation in logic synthesis. A function f(X) is bi-decomposable under a variable partition XA, XB, XC on X if it can be written...
Ruei-Rung Lee, Jie-Hong Roland Jiang, Wei-Lun Hung
DAC
2008
ACM
16 years 7 months ago
Driver waveform computation for timing analysis with multiple voltage threshold driver models
This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs...
Peter Feldmann, Soroush Abbaspour, Debjit Sinha, G...
DAC
2008
ACM
16 years 7 months ago
A MIPS R2000 implementation
Nathaniel Ross Pinckney, Thomas Barr, Michael Dayr...
DAC
2008
ACM
16 years 7 months ago
TuneFPGA: post-silicon tuning of dual-Vdd FPGAs
Modern CMOS manufacturing processes have significant variability, which necessitates guard banding to achieve reasonable yield. We study an FPGA architecture with a dual voltage s...
Stephen Bijansky, Adnan Aziz
DAC
2008
ACM
16 years 7 months ago
Formal datapath representation and manipulation for implementing DSP transforms
We present a domain-specific approach to representing datapaths for hardware implementations of linear signal transform algorithms. We extend the tensor structure for describing l...
Franz Franchetti, James C. Hoe, Markus Püsche...