Sciweavers

175
Voted
DAC
2009
ACM
16 years 7 months ago
Evaluating design trade-offs in customizable processors
The short time-to-market window for embedded systems demands automation of design methodologies for customizable processors. Recent research advances in this direction have mostly...
Unmesh D. Bordoloi, Huynh Phung Huynh, Samarjit Ch...
DAC
2009
ACM
16 years 7 months ago
ILP-based pin-count aware design methodology for microfluidic biochips
Digital microfluidic biochips have emerged as a popular alternative for laboratory experiments. To make the biochip feasible for practical applications, pin-count reduction is a k...
Cliff Chiung-Yu Lin, Yao-Wen Chang
DAC
2009
ACM
16 years 7 months ago
O-Router:an optical routing framework for low power on-chip silicon nano-photonic integration
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices...
Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, D...
DAC
2009
ACM
16 years 7 months ago
BDD-based synthesis of reversible logic for large functions
Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like low-pow...
Robert Wille, Rolf Drechsler
DAC
2009
ACM
16 years 7 months ago
Retiming and recycling for elastic systems with early evaluation
Retiming and recycling are two transformations used to optimize the performance of latency-insensitive (a.k.a. synchronous elastic) systems. This paper presents an approach that c...
Dmitry Bufistov, Jordi Cortadella, Marc Galceran O...
DAC
2009
ACM
16 years 7 months ago
Speculation in elastic systems
Speculation is a well-known technique for increasing parallelism of the microprocessor pipelines and hence their performance. While implementing speculation in modern design pract...
Marc Galceran Oms, Jordi Cortadella, Michael Kishi...
136
Voted
DAC
2009
ACM
16 years 7 months ago
Flip-chip routing with unified area-I/O pad assignments for package-board co-design
In this paper, we present a novel flip-chip routing algorithm for package-board co-design. Unlike the previous works that can consider only either free- or pre-assignment routing,...
Jia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang
DAC
2009
ACM
16 years 7 months ago
Interconnection fabric design for tracing signals in post-silicon validation
Post-silicon validation has become an essential step in the design flow of today's complex integrated circuits. One effective technique that provides real-time visibility to ...
Xiao Liu, Qiang Xu
DAC
2009
ACM
16 years 7 months ago
Online cache state dumping for processor debug
Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, fo...
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishna...