Sciweavers

DAC
2009
ACM
16 years 7 months ago
A robust and efficient harmonic balance (HB) using direct solution of HB Jacobian
In this paper we introduce a new method of performing direct solution of the harmonic balance Jacobian. For examples with moderate number of harmonics and moderate to strong nonli...
Amit Mehrotra, Abhishek Somani
DAC
2009
ACM
16 years 7 months ago
Efficient design-specific worst-case corner extraction for integrated circuits
Hong Zhang, Tsung-Hao Chen, Ming Yuan Ting, Xin Li
DAC
2009
ACM
16 years 7 months ago
Timing-driven optimization using lookahead logic circuits
This paper describes a function-based timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the principles of parallel prefix computat...
Mihir R. Choudhury, Kartik Mohanram
153
Voted
DAC
2009
ACM
16 years 7 months ago
Matching-based minimum-cost spare cell selection for design changes
Metal-only ECO realizes the last-minute design changes by revising the photomasks of metal layers only. This task is challenging because the pre-injected spare cells are limited b...
Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, H...
DAC
2009
ACM
16 years 7 months ago
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
DAC
2009
ACM
16 years 7 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert
DAC
2009
ACM
16 years 7 months ago
Spare-cell-aware multilevel analytical placement
Post-silicon validation has recently drawn designers' attention due to its increasing impacts on the VLSI design cycle and cost. One key feature of the post-silicon validatio...
Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yu...
DAC
2009
ACM
16 years 7 months ago
Handling complexities in modern large-scale mixed-size placement
In this paper, we propose an effective algorithm flow to handle largescale mixed-size placement. The basic idea is to use floorplanning to guide the placement of objects at the gl...
Jackey Z. Yan, Natarajan Viswanathan, Chris Chu
DAC
2009
ACM
16 years 7 months ago
Spectral techniques for high-resolution thermal characterization with limited sensor data
Elevated chip temperatures are true limiters to the scalability of computing systems. Excessive runtime thermal variations compromise the performance and reliability of integrated...
Ryan Cochran, Sherief Reda
DAC
2009
ACM
16 years 7 months ago
Dynamic thermal management via architectural adaptation
Exponentially rising cooling/packaging costs due to high power density call for architectural and software-level thermal management. Dynamic thermal management (DTM) techniques co...
Ramkumar Jayaseelan, Tulika Mitra