5 search results - page 1 / 1 » A New Design for Double Edge Triggered Flip-flops |
ASPDAC
2006
ACM
14 years 4 months ago
2006
ACM
In this paper, a new flip-flop called Double-edge triggered Feedback Flip-Flop (DFFF) is proposed. The dynamic power consumption of DFFF is reduced by avoiding unnecessary interna...
ASPDAC
1998
ACM
14 years 3 months ago
1998
ACM
-- The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET fl...
TCAD
2010
13 years 5 months ago
2010
Abstract--In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different ex...
ICCAD
2004
IEEE
14 years 7 months ago
2004
IEEE
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...
CHI
1998
ACM
14 years 3 months ago
1998
ACM
This paper presents a system for interacting with digital information, called Triangles. The Triangles system is a physical/digital construction kit, which allows users to use two...