Simultaneous Analytic Area and Power Optimization for Repeater Insertion

We present an analytic formula for repeater insertion in global interconnects that simultaneously minimizes silicon device area and power dissipation for a given performance qrj,/K where 7cr,, is the minimum possible delay along a global interconnect, with

• Type: Conference
• Year: 2003
• Where: ICCAD
• Authors: Giuseppe S. Garcea, N. P. van der Meijs, Ralph H. J. M. Otten
• Keywords: Global Interconnects, Hardware, ICCAD 2003, Minimum Possible Delay, Silicon Device Area