135
Voted
ICCD
15 years 11 months ago
2004 IEEE 
Research in high-speed interconnect requires physical test to validate circuit models and design assumptions. At multi-Gbit/sec rates, physical implementations require custom circ...
129
Voted
ICCD
15 years 11 months ago
2004 IEEE
Compared are different methods for evaluation of formulas expressing microprocessor correctness in the logic of Equality with Uninterpreted Functions and Memories (EUFM) by transl...
129
Voted
ICCD
15 years 11 months ago
2004 IEEE
Networks-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnect problems. NoC architecture consists of a collection of IP core...
127
Voted
ICCD
15 years 11 months ago
2004 IEEE 
Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation. However, with progress...
126
Voted
ICCD
15 years 11 months ago
2004 IEEE
A negative effect of ever-shrinking supply and threshold voltages is the larger percentage of total power consumption that comes from leakage current. Several techniques have been...
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Hardware