Sciweavers

186 search results - page 24 / 38
» 1995 high level synthesis design repository
Sort
View
ECTEL
2007
Springer
14 years 1 months ago
MACE - Enriching Architectural Learning Objects for Experience Multiplication
Education in architecture requires access to a broad range of learning materials to develop flexibility and creativity in design. The learning material is compromised of textual an...
Moritz Stefaner, Elisa Dalla Vecchia, Massimiliano...
DATE
2002
IEEE
206views Hardware» more  DATE 2002»
14 years 19 days ago
Accurate Area and Delay Estimators for FPGAs
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
Anshuman Nayak, Malay Haldar, Alok N. Choudhary, P...
SEUS
2008
IEEE
14 years 2 months ago
Model Based Synthesis of Embedded Software
Abstract— This paper presents SW synthesis using Embedded System Environment (ESE), a tool set for design of multicore embedded systems. We propose a classification of multicore...
Daniel D. Gajski, Samar Abdi, Ines Viskic
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 8 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
14 years 28 days ago
A novel improvement technique for high-level test synthesis
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jaha...