186 search results - page 32 / 38 » 1995 high level synthesis design repository |
AADEBUG
2005
Springer
14 years 1 months ago
2005
Springer
Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism. In our solution to this problem, features are inserted into the u...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
FPGA
2009
ACM
14 years 2 months ago
2009
ACM
We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is cap...
FMCAD
2007
Springer
13 years 11 months ago
2007
Springer
Modeling hardware through atomic guard/action transitions with interleaving semantics is popular, owing to the conceptual clarity of modeling and verifying the high level behavior ...
SIGGRAPH
1995
ACM
13 years 11 months ago
1995
ACM
Artistic screening is a new image reproduction technique incorporatingfreelycreatedartisticscreenelementsforgeneratinghalftones. Fixed predefined dot contours associated with giv...