186 search results - page 4 / 38 » 1995 high level synthesis design repository |
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
In this paper we describe, a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire del...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
ISLPED
1997
ACM
13 years 11 months ago
1997
ACM
With the increasing performance and density of VLSI circuits as well as the popularity of portable devices such as personal digital assistance, power consumption has emerged as an...