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» A Congestion Driven Placement Algorithm for FPGA Synthesis
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ISPD
2009
ACM
141views Hardware» more  ISPD 2009»
14 years 2 months ago
A faster approximation scheme for timing driven minimum cost layer assignment
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
Shiyan Hu, Zhuo Li, Charles J. Alpert
DAC
2009
ACM
14 years 8 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert
DAC
2003
ACM
14 years 8 months ago
Dynamic hardware/software partitioning: a first approach
Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy co...
Greg Stitt, Roman L. Lysecky, Frank Vahid
GCB
2006
Springer
158views Biometrics» more  GCB 2006»
13 years 11 months ago
Microarray Layout as Quadratic Assignment Problem
Abstract: The production of commercial DNA microarrays is based on a light-directed chemical synthesis driven by a set of masks or micromirror arrays. Because of the natural proper...
Sérgio A. de Carvalho, Sven Rahmann
FPL
2003
Springer
113views Hardware» more  FPL 2003»
14 years 20 days ago
Data Dependent Circuit Design: A Case Study
Abstract. Data dependent circuits are logic circuits specialized to specific input data. They are smaller and faster than the original circuits, although they are not reusable and...
Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto