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ICCAD
2008
IEEE
116views Hardware» more  ICCAD 2008»
14 years 6 months ago
Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example
—Connecting system-level performance models with circuit information has been a long-standing problem in analog/mixed-signal front-ends, like radios and high-speed links. High-sp...
Ranko Sredojevic, Vladimir Stojanovic
ICCAD
2007
IEEE
108views Hardware» more  ICCAD 2007»
14 years 6 months ago
Novel wire density driven full-chip routing for CMP variation control
— As nanometer technology advances, the post-CMP dielectric thickness variation control becomes crucial for manufacturing closure. To improve CMP quality, dummy feature filling ...
Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-...
ICCAD
2005
IEEE
100views Hardware» more  ICCAD 2005»
14 years 6 months ago
Performance-centering optimization for system-level analog design exploration
In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog ...
Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih C...
ICCAD
2004
IEEE
125views Hardware» more  ICCAD 2004»
14 years 6 months ago
Temporal floorplanning using the T-tree formulation
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we model each task ...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
ICCAD
2001
IEEE
126views Hardware» more  ICCAD 2001»
14 years 6 months ago
Constraint Satisfaction for Relative Location Assignment and Scheduling
Tight data- and timing constraints are imposed by communication and multimedia applications. The architecture for the embedded processor imply resource constraints. Instead of ran...
Carlos A. Alba Pinto, Bart Mesman, Jochen A. G. Je...