714 search results - page 11 / 143 » A Decompression Architecture for Low Power Embedded Systems |
DCC
2000
IEEE
13 years 12 months ago
2000
IEEE
We present a novel algorithm that assigns codes to instructions during instruction code compression in order to minimize bus-related bit-toggling and thus reducing power consumpti...
SOSP
2001
ACM
14 years 4 months ago
2001
ACM
In recent years, there has been a rapid and wide spread of nontraditional computing platforms, especially mobile and portable computing devices. As applications become increasingl...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— Traditional level-one instruction caches and data caches for embedded systems typically have the same capacities. Configurable caches either shut down a part of the cache to su...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
IJPP
2007
13 years 7 months ago
2007
