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» A Decompression Architecture for Low Power Embedded Systems
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ASPDAC
2007
ACM
156views Hardware» more  ASPDAC 2007»
14 years 22 days ago
Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Archit
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
Zahid Khan, Tughrul Arslan
ISVLSI
2006
IEEE
114views VLSI» more  ISVLSI 2006»
14 years 2 months ago
A Low Power Lookup Technique for Multi-Hashing Network Applications
Many network security applications require large virus signature sets to be maintained, retrieved, and compared against the network streams. Software applications frequently fail ...
Ilhan Kaya, Taskin Koçak
ASPDAC
2006
ACM
116views Hardware» more  ASPDAC 2006»
14 years 2 months ago
Abridged addressing: a low power memory addressing strategy
Abstract— The memory subsystem is known to comprise a significant fraction of the power dissipation in embedded systems. The memory addressing strategy, which determines the seq...
Preeti Ranjan Panda
ICCD
2002
IEEE
228views Hardware» more  ICCD 2002»
14 years 5 months ago
JMA: The Java-Multithreading Architecture for Embedded Processors
Embedded processors are increasingly deployed in applications requiring high performance with good real-time characteristics whilst being low power. Parallelism has to be extracte...
Panit Watcharawitch, Simon W. Moore
TVLSI
1998
109views more  TVLSI 1998»
13 years 8 months ago
Power estimation of embedded systems: a hardware/software codesign approach
— The need for low-power embedded systems has become very significant within the microelectronics scenario in the most recent years. A power-driven methodology is mandatory duri...
William Fornaciari, Paolo Gubian, Donatella Sciuto...