103 search results - page 8 / 21 » A Fault Modeling Technique to Test Memory BIST Algorithms |
120
Voted
DATE
2002
IEEE
15 years 9 months ago
2002
IEEE
Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of eac...
137
Voted
ATS
2009
IEEE
15 years 9 months ago
2009
IEEE
Caches are crucial components in modern processors (both stand-alone or integrated into SoCs) and their test is a challenging task, especially when addressing complex and high-fre...
144
Voted
DAC
2009
ACM
16 years 5 months ago
2009
ACM
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
133
Voted
VLSID
2009
IEEE
16 years 4 months ago
2009
IEEE
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
122
click to vote
ITC
2002
IEEE
15 years 8 months ago
2002
IEEE
The advantage to “one test at a time” fault diagnosis is its ability to implicate the components of complicated defect behaviors. The disadvantage is the large size and opacit...