189 search results - page 3 / 38 » A Functional DBPL Revealing High Level Optimizations |
ISLPED
2005
ACM
14 years 12 days ago
2005
ACM
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
ICCD
2004
IEEE
14 years 3 months ago
2004
IEEE
Compared are different methods for evaluation of formulas expressing microprocessor correctness in the logic of Equality with Uninterpreted Functions and Memories (EUFM) by transl...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
IWPC
2000
IEEE
13 years 11 months ago
2000
IEEE
This paper presents a framework for software architecture recovery and restructuring. The user specifies a high level abstraction view of the system using a structured pattern la...
TPCTC
2010
Springer
13 years 1 months ago
2010
Springer
Abstract. Event Processing (EP) systems are being progressively used in business critical applications in domains such as algorithmic trading, supply chain management, production m...