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» A Graph Reduction Approach to Symbolic Circuit Analysis
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ISQED
2006
IEEE
147views Hardware» more  ISQED 2006»
14 years 1 months ago
Compact Reduced Order Modeling for Multiple-Port Interconnects
— In this paper, we propose an efficient model order reduction (MOR) algorithm, called MTermMOR, for modeling interconnect circuits with large number of external ports. The prop...
Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng ...
ICCAD
1999
IEEE
86views Hardware» more  ICCAD 1999»
13 years 12 months ago
A framework for testing core-based systems-on-a-chip
Available techniques for testing core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesising low-overhead test architectures and compact test solutions....
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jh...
SIAMSC
2008
140views more  SIAMSC 2008»
13 years 7 months ago
Compact Fourier Analysis for Designing Multigrid Methods
The convergence of Multigrid methods can be analyzed based on a Fourier analysis of the method or by proving certain inequalities that have to be fulfilled by the smoother and by t...
Thomas K. Huckle
ASPDAC
2005
ACM
131views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Analysis of buffered hybrid structured clock networks
- This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical...
Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheld...
ICCAD
2003
IEEE
195views Hardware» more  ICCAD 2003»
14 years 25 days ago
Vectorless Analysis of Supply Noise Induced Delay Variation
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
Sanjay Pant, David Blaauw, Vladimir Zolotov, Savit...