6 search results - page 1 / 2 » A Heuristic for Clock Selection in High-Level Synthesis |
VLSID
2002
IEEE
14 years 11 months ago
2002
IEEE
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
ISSS
1996
IEEE
14 years 3 months ago
1996
IEEE
ASPDAC
2008
ACM
14 years 27 days ago
2008
ACM
We propose REWIRED (REgister Write Inhibition by REsource Dedication), a technique for reducing power during high level synthesis (HLS) by selectively inhibiting the storage of fun...
ISLPED
2003
ACM
14 years 4 months ago
2003
ACM
This paper proposes two very fast graph theoretic heuristics for the low power binding problem given fixed number of resources and multiple architectures for the resources. First...
FCCM
2011
IEEE
13 years 2 months ago
2011
IEEE
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...