110 search results - page 9 / 22 » A Highly-Configurable Cache Architecture for Embedded System... |
GLVLSI
2005
IEEE
14 years 2 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
With the ongoing advancements in VLSI technology, the performance of an embedded system is determined to a large extend by the communication of data and instructions. This results...
JTRES
2010
ACM
13 years 8 months ago
2010
ACM
In order to guarantee that real-time systems meet their timing specification, static execution time bounds need to be calculated. Not considering execution time predictability led...
ICCD
2004
IEEE
14 years 5 months ago
2004
IEEE
This paper proposes a power-aware cache block allocation algorithm for the way-selective setassociative cache on embedded systems to reduce energy consumption without additional d...
GLVLSI
2010
IEEE
13 years 10 months ago
2010
IEEE
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...