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» A Logical Viewpoint on Architectures
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FPL
2004
Springer
101views Hardware» more  FPL 2004»
14 years 4 months ago
Automatic Creation of Reconfigurable PALs/PLAs for SoC
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run -time reconfigurabil...
Mark Holland, Scott Hauck
ITC
2003
IEEE
158views Hardware» more  ITC 2003»
14 years 4 months ago
Extraction Error Diagnosis and Correction in High-Performance Designs
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikara...
APPT
2003
Springer
14 years 4 months ago
Scheduling Outages in Distributed Environments
This paper focuses on the problem of scheduling outages to computer systems in complex distributed environments. The interconnected nature of these systems makes scheduling global ...
Anthony Butler, Hema Sharda, David Taniar
FPL
2003
Springer
81views Hardware» more  FPL 2003»
14 years 4 months ago
Software Decelerators
This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...
Eric Keller, Gordon J. Brebner, Philip James-Roxby
ASAP
2002
IEEE
103views Hardware» more  ASAP 2002»
14 years 3 months ago
PAPA - Packed Arithmetic on a Prefix Adder for Multimedia Applications
This paper introduces PAPA: Packed Arithmetic on a Prefix Adder, a new approach to parallel prefix adder design that supports a wide variety of packed arithmetic computations, inc...
Neil Burgess