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HPCA
2008
IEEE
14 years 8 months ago
Regional congestion awareness for load balance in networks-on-chip
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
Paul Gratz, Boris Grot, Stephen W. Keckler
HPCA
2006
IEEE
14 years 8 months ago
Efficient instruction schedulers for SMT processors
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
Joseph J. Sharkey, Dmitry V. Ponomarev
HPCA
2005
IEEE
14 years 8 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
SIGMOD
2006
ACM
156views Database» more  SIGMOD 2006»
14 years 8 months ago
MauveDB: supporting model-based user views in database systems
Real-world data -- especially when generated by distributed measurement infrastructures such as sensor networks -- tends to be incomplete, imprecise, and erroneous, making it impo...
Amol Deshpande, Samuel Madden
ICCAD
2005
IEEE
147views Hardware» more  ICCAD 2005»
14 years 4 months ago
NoCEE: energy macro-model extraction methodology for network on chip routers
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
Jeremy Chan, Sri Parameswaran