49 search results - page 5 / 10 » A Low Power Charge-Recycling CMOS Clock Buffer |
CCECE
2006
IEEE
14 years 20 days ago
2006
IEEE
A high-speed low-power rail-to-rail class-B buffer amplifier, which is suitable for liquid crystal display applications, is proposed. The summing circuit is biased by the constant...
DSD
2006
IEEE
14 years 19 days ago
2006
IEEE
The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper we present an AES encryption h...
APCCAS
2006
IEEE
14 years 20 days ago
2006
IEEE
Abstract— This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and...
TVLSI
2010
13 years 1 months ago
2010
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
ISLPED
2005
ACM
14 years 4 days ago
2005
ACM
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...