26 search results - page 4 / 6 » A Low-Power Cache Design for CalmRISCTM-Based Systems |
ISLPED
2005
ACM
14 years 27 days ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
DATE
2000
IEEE
13 years 11 months ago
2000
IEEE
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
MICRO
1997
IEEE
13 years 11 months ago
1997
IEEE
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
CF
2011
ACM
12 years 7 months ago
2011
ACM
Ubiquitous computing has become a very popular paradigm. The most suitable technological solution for those systems consists of using hybrid processors able to operate at high vol...
GLVLSI
2005
IEEE
14 years 29 days ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...