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VLSISP
2008
147views more  VLSISP 2008»
13 years 6 months ago
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sun...
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
14 years 2 months ago
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware a...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
DATE
1999
IEEE
81views Hardware» more  DATE 1999»
14 years 20 hour ago
A Power Estimation Model for High-Speed CMOS A/D Converters
Power estimation is important for system-level exploration and trade-off analysis of VLSI systems. A power estimator for high-speed analog to digital converters that exploits info...
Erik Lauwers, Georges G. E. Gielen
ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
14 years 4 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha
ISSS
2002
IEEE
176views Hardware» more  ISSS 2002»
14 years 19 days ago
Controller Estimation for FPGA Target Architectures during High-Level Synthesis
In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence,...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...