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» A Methodology for Large-Scale Hardware Verification
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ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 10 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
ICCD
2008
IEEE
119views Hardware» more  ICCD 2008»
16 years 2 months ago
Hierarchical simulation-based verification of Anton, a special-purpose parallel machine
—One of the major design verification challenges in the development of Anton, a massively parallel special-purpose machine for molecular dynamics, was to provide evidence that co...
John P. Grossman, John K. Salmon, Richard C. Ho, D...
161
Voted
DAC
2003
ACM
16 years 6 months ago
Death, taxes and failing chips
In the way they cope with variability, present-day methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important as...
Chandu Visweswariah
FMSD
2002
107views more  FMSD 2002»
15 years 5 months ago
Verification of Out-Of-Order Processor Designs Using Model Checking and a Light-Weight Completion Function
We present a new technique for verification of complex hardware devices that allows both generality andahighdegreeofautomation.Thetechniqueisbasedonournewwayofconstructinga"li...
Sergey Berezin, Edmund M. Clarke, Armin Biere, Yun...
123
Voted
ICCAD
2006
IEEE
93views Hardware» more  ICCAD 2006»
16 years 2 months ago
Precise identification of the worst-case voltage drop conditions in power grid verification
– Identifying worst-case voltage drop conditions in every module supplied by the power grid is a crucial problem in modern IC design. In this paper we develop a novel methodology...
Nestoras E. Evmorfopoulos, Dimitris P. Karampatzak...