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IOLTS
2006
IEEE
103views Hardware» more  IOLTS 2006»
14 years 1 months ago
Designing Robust Checkers in the Presence of Massive Timing Errors
So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerb...
Frederic Worm, Patrick Thiran, Paolo Ienne
DAC
2006
ACM
14 years 8 months ago
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty
Existing approaches to timing analysis under uncertainty are based on restrictive assumptions. Statistical STA techniques assume that the full probabilistic distribution of parame...
Wei-Shen Wang, Vladik Kreinovich, Michael Orshansk...
IJCV
2006
116views more  IJCV 2006»
13 years 7 months ago
Structure-Texture Image Decomposition - Modeling, Algorithms, and Parameter Selection
This paper explores various aspects of the image decomposition problem using modern variational techniques. We aim at splitting an original image f into two components u and v, whe...
Jean-François Aujol, Guy Gilboa, Tony F. Ch...
VTS
2008
IEEE
119views Hardware» more  VTS 2008»
14 years 1 months ago
Error Sequence Analysis
With increasing IC process variation and increased operating speed, it is more likely that even subtle defects will lead to the malfunctioning of a circuit. Various fault models, ...
Jaekwang Lee, Intaik Park, Edward J. McCluskey
DAC
1999
ACM
13 years 11 months ago
Model Order-Reduction of RC(L) Interconnect Including Variational Analysis
As interconnect feature sizes continue to scale to smaller dimensions, long interconnect can dominate the IC timing performance, but the interconnect parameter variations make it ...
Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas