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ISSS
1995
IEEE
100views Hardware» more  ISSS 1995»
14 years 6 hour ago
Power analysis and low-power scheduling techniques for embedded DSP software
This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been dev...
Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, M...
CODES
2008
IEEE
14 years 2 months ago
Intra- and inter-processor hybrid performance modeling for MPSoC architectures
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid perfor...
Frank E. B. Ophelders, Samarjit Chakraborty, Henk ...
ISCA
2011
IEEE
229views Hardware» more  ISCA 2011»
13 years 5 days ago
TLSync: support for multiple fast barriers using on-chip transmission lines
As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament ba...
Jungju Oh, Milos Prvulovic, Alenka G. Zajic
IROS
2009
IEEE
170views Robotics» more  IROS 2009»
14 years 3 months ago
A programming architecture for smart autonomous underwater vehicles
— Autonomous underwater vehicles (AUVs) are an indispensable tool for marine scientists to study the world’s oceans. The Slocum glider is a buoyancy driven AUV designed for mis...
Hans C. Woithe, Ulrich Kremer
ECRTS
2000
IEEE
14 years 26 days ago
Towards validated real-time software
We present a tool for the design and validation of embedded real-time applications. The tool integrates two approaches, the use of the synchronous programming language ESTEREL for...
Valérie Bertin, Michel Poize, Jacques Pulou...