36 search results - page 4 / 8 » A Near Optimal Algorithm for Technology Mapping Minimizing A... |
TCAD
2010
13 years 1 months ago
2010
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...
ICCAD
1994
IEEE
13 years 10 months ago
1994
IEEE
We propose a technology mapping algorithm that takes existing structural technology-mapping algorithms based on dynamic programming [1,3,4] and extends them to retime pipelined cir...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
ISLPED
2003
ACM
13 years 12 months ago
2003
ACM
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous a...
GLVLSI
2006
IEEE
14 years 19 days ago
2006
IEEE
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...