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» A New Approach for Low Power Scan Testing
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DAC
2005
ACM
13 years 9 months ago
Multi-frequency wrapper design and optimization for embedded cores under average power constraints
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty
DDECS
2007
IEEE
201views Hardware» more  DDECS 2007»
14 years 1 months ago
Built in Defect Prognosis for Embedded Memories
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskaran...
ICC
2007
IEEE
14 years 1 months ago
A New Trellis Shaping Approach for Pulse-Shaped PSK Signals with Almost Constant Envelope
—In this paper, a novel peak power reduction scheme based on trellis shaping is proposed for single-carrier pulseshaped phase shift keying (PSK) systems. The use of PSK generally...
Makoto Tanahashi, Hideki Ochiai
ITC
2000
IEEE
76views Hardware» more  ITC 2000»
13 years 11 months ago
System issues in boundary-scan board test
Boards have evolved into complex systems and even collections of interacting systems. Test engineers struggle to find out how these systems are initialized and booted because of p...
Kenneth P. Parker
ITC
1996
IEEE
127views Hardware» more  ITC 1996»
13 years 11 months ago
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
Nur A. Touba, Edward J. McCluskey