Sciweavers

32 search results - page 4 / 7
» A New High Density and Very Low Cost Reprogrammable FPGA Arc...
Sort
View
ARC
2009
Springer
134views Hardware» more  ARC 2009»
14 years 1 months ago
A HyperTransport 3 Physical Layer Interface for FPGAs
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
Heiner Litz, Holger Fröning, Ulrich Brün...
DATE
2009
IEEE
155views Hardware» more  DATE 2009»
14 years 3 months ago
Dynamic thermal management in 3D multicore architectures
— Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architec...
Ayse Kivilcim Coskun, José L. Ayala, David ...
CODES
2003
IEEE
14 years 1 months ago
A low-cost memory architecture with NAND XIP for mobile embedded systems
NAND flash memory has become an indispensable component in mobile embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cost and ...
Chanik Park, Jaeyu Seo, Sunghwan Bae, Hyojun Kim, ...
EMSOFT
2008
Springer
13 years 10 months ago
A PRAM and NAND flash hybrid architecture for high-performance embedded storage subsystems
NAND flash-based storage is widely used in embedded systems due to its numerous benefits: low cost, high density, small form factor and so on. However, NAND flash-based storage is...
Jin Kyu Kim, Hyung Gyu Lee, Shinho Choi, Kyoung Il...
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
14 years 2 months ago
Networks on chips for high-end consumer-electronics TV system architectures
Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SO...
Frits Steenhof, Harry Duque, Björn Nilsson, K...