Sciweavers

509 search results - page 49 / 102
» A New Multiport Memory for High Performance Parallel Process...
Sort
View
EMSOFT
2005
Springer
14 years 2 months ago
Optimizing inter-processor data locality on embedded chip multiprocessors
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
Guilin Chen, Mahmut T. Kandemir
IEEEPACT
2007
IEEE
14 years 3 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
DATE
2008
IEEE
171views Hardware» more  DATE 2008»
14 years 3 months ago
Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
Arno Moonen, Marco Bekooij, Rene van den Berg, Jef...
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 1 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
LCPC
2007
Springer
14 years 3 months ago
Automatic Communication Performance Debugging in PGAS Languages
Recent studies have shown that programming in a Partition Global Address Space (PGAS) language can be more productive than programming in a message passing model. One reason for th...
Jimmy Su, Katherine A. Yelick