522 search results - page 14 / 105 » A Note on Designing Logical Circuits Using SAT |
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
VTS
2000
IEEE
13 years 11 months ago
2000
IEEE
ESIM is a simulation tool that integrates logic fault and design error simulation for logic circuits. It targets several design error and fault models, and uses a novel mix of sim...
SBCCI
2006
ACM
14 years 1 months ago
2006
ACM
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full...
ISMVL
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01)asynchronous circuits. It is shown that fully DIasynchronous cir...
FPT
2005
IEEE
14 years 28 days ago
2005
IEEE
Producing a functionally correct integrated circuit is becoming increasingly difficult. No matter how careful a designer is, there will always be integrated circuits that are fabr...