522 search results - page 34 / 105 » A Note on Designing Logical Circuits Using SAT |
VLSID
2005
IEEE
14 years 7 months ago
2005
IEEE
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
ITC
1994
IEEE
13 years 11 months ago
1994
IEEE
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
Abstract— Over the last decade, the design of ultra-lowpower digital circuits in subthreshold regime has been driven by the quest for minimum energy per operation. In this contri...
JUCS
2007
13 years 7 months ago
2007
: It is a difficult problem that using cellular neural network to make up of analog signal processing circuit. This paper presented the architecture of new cellular neural network ...
ASPDAC
1998
ACM
13 years 11 months ago
1998
ACM
ABSTRACT - This paper presents a new design flow, FPDSiMPA, and a set of techniques for synthesizing high-performance sub-half micron logic circuits. FPD-SiMPA consists of logic p...