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» A Note on Designing Logical Circuits Using SAT
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FPGA
2009
ACM
180views FPGA» more  FPGA 2009»
14 years 4 months ago
Scalable don't-care-based logic optimization and resynthesis
We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is cap...
Alan Mishchenko, Robert K. Brayton, Jie-Hong Rolan...
DAC
2007
ACM
14 years 10 months ago
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characte...
Kunhyuk Kang, Kee-Jong Kim, Ahmad E. Islam, Muhamm...
FPGA
1998
ACM
140views FPGA» more  FPGA 1998»
14 years 2 months ago
More Wires and Fewer LUTs: A Design Methodology for FPGAs
In designing FPGAs, it is important to achieve a good balance between the number of logic blocks, such as Look-Up Tables (LUTs), and wiring resources. It is dicult to nd an optim...
Atsushi Takahara, Toshiaki Miyazaki, Takahiro Muro...
DAC
2007
ACM
14 years 10 months ago
On-The-Fly Resolve Trace Minimization
The ability of modern SAT solvers to produce proofs of unsatisfiability for Boolean formulas has become a powerful tool for EDA applications. Proofs are generated from a resolve t...
Ohad Shacham, Karen Yorav
DAC
2006
ACM
14 years 10 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang