522 search results - page 75 / 105 » A Note on Designing Logical Circuits Using SAT |
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
TCAD
1998
13 years 7 months ago
1998
Conventional scan design imposes considerable area and delay overhead by using larger scan
ip-
ops and additional scan wires without utilizing the functionality of the combinatio...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Negative Bias Temperature Instability (NBTI), a PMOS aging phenomenon causing significant loss on circuit performance and lifetime, has become a critical challenge for temporal re...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
The sequential depth determines the completeness of bounded model checking in design verification. Recently, a SATbased method is proposed to compute the sequential depth of a de...
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
: Double-Gate (DG) transistors have emerged as promising devices for nano-scale circuits due to their better scalability compared to bulk CMOS. Among the various types of DG device...